 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| ltp 5901- ipm / ltp 5902- ipm 1 59012ipmfa for more information www.linear.com/ltp5901-ipm or www.linear.com/ltp5902-ipm typical application network features description smartmesh ip node 2.4ghz 802.15.4e wireless mote module smartmesh ip? wireless sensor networks are self man- aging, low power internet protocol ( ip) networks built from wireless nodes called motes. the lt p ?5901-ipm/ lt p 5902-ipm is the ip mote product in the eterna ? * family of ieee 802.15.4 e printed circuit board assembly solutions , featuring a highly-integrated, low power radio design by dust networks ? as well as an arm cortex-m 3 32- bit microprocessor running dusts embedded smartmesh ip networking software. both the lt p 5901-ipm ( with chip antenna), at 24 mm 42 mm, and the lt p 5902-ipm ( with mmcx connector), at 24 mm 37 mm, are designed for surface mount assembly. with dusts time-synchronized smartmesh ip networks, all motes in the network may route, source or terminate data, while providing many years of battery powered operation. the smartmesh ip software provided with the lt p 5901-ipm/ lt p 5902-ipm is fully tested and validated, and is readily configured via a software application pro - gramming interface. smartmesh ip motes deliver a highly flexible network with proven reliability and low power performance in an easy-to-integrate platform. ltp 5901- ipm / ltp 5902- ipm features n complete radio transceiver , embedded processor , and networking software for forming a self-healing mesh network n smartmesh ? networks incorporate: n time synchronized network-wide scheduling n per transmission frequency hopping n redundant spatially diverse topologies n network-wide reliability and power optimization n nist certified security n smartmesh networks deliver: n >99.999% network reliability achieved in the most challenging rf environments n sub 50a routing nodes n compliant to 6lowpan internet protocol (ip) and ieee 802.15.4e standards n industry-leading low power radio technology with 4.5ma to receive and 9.7ma to transmit at 8dbm n rf modular certification include usa, canada, eu , japan, taiwan, korea, india, australia and new zealand n pcb assembly with chip antenna ( lt p 5901-ipm) or with mmcx antenna connector ( lt p 5902-ipm). qfn version ( lt c ? 5800-ipm) available n micrium cos-ii real time operating system based on-chip software development kit l , lt , lt c , lt m , linear technology, the linear logo, dust, dust networks, smartmesh and eterna are registered trademarks and lt p , the dust networks logo and smartmesh ip are trademarks of linear technology corporation. all other trademarks are the property of their respective owners. protected by u.s. patents, including 7375594, 7420980, 7529217, 7791419, 7881239, 7898322, 8222965. * eterna is dust networks low power radio soc architecture. 59012ipm ta01 controller sensor in+inC spi ltc2379-18 ltp5901-ipr/ ltp5902-ipr uart antenna host application uart ltp5901-ipm downloaded from: http:///
ltp 5901- ipm / ltp 5902- ipm 2 59012ipmfa for more information www.linear.com/ltp5901-ipm or www.linear.com/ltp5902-ipm table of contents network features .......................................... 1 ltp5901-ipm/ltp5902-ipm features ................... 1 typical application ........................................ 1 description.................................................. 1 table of contents .......................................... 2 smartmesh network overview ........................... 3 absolute maximum ratings .............................. 4 pin configuration .......................................... 4 order information .......................................... 5 recommended operating conditions ................... 5 dc characteristics ......................................... 5 radio specifications ...................................... 6 radio receiver characteristics .......................... 6 radio transmitter characteristics ....................... 7 digital i/o characteristics ................................ 7 temperature sensor characteristics .................... 8 analog input chain characteristics ..................... 8 system characteristics ................................... 8 uart ac characteristics .................................. 9 timen ac characteristics ................................ 10 radio_inhibit ac characteristics ....................... 10 flash ac characteristics ................................. 11 flash spi slave ac characteristics .................... 11 spi master ac characteristics .......................... 12 i 2 c ac characteristics .................................... 13 1-wire master ............................................. 13 flash spi slave ac characteristics .................... 14 typical performance characteristics .................. 15 pin functions .............................................. 20 operation................................................... 24 power supply .......................................................... 24 supply monitoring and reset ................................. 25 precision timing ..................................................... 25 application time synchronization .......................... 25 time references ..................................................... 25 radio ...................................................................... 26 uarts ..................................................................... 26 autonomous mac ................................................... 27 security .................................................................. 27 temperature sensor ............................................... 27 radio inhibit ....................................................... 27 software installation ............................................... 27 flash data retention ............................................... 28 state diagram ......................................................... 28 i 2 c master .............................................................. 30 spi master .............................................................. 30 1-wire master ......................................................... 30 applications information ................................ 31 modes of operation ................................................ 31 regulatory and standards compliance ................... 31 soldering information ............................................. 32 related documentation .................................. 32 package description ..................................... 33 revision history .......................................... 35 typical application ....................................... 36 related parts .............................................. 36 downloaded from: http:/// ltp 5901- ipm / ltp 5902- ipm 3 59012ipmfa for more information www.linear.com/ltp5901-ipm or www.linear.com/ltp5902-ipm smartmesh network overview the network manager uses health reports to continually optimize the network to maintain >99.999% data reliability even in the most challenging rf environments. the use of tsch allows smartmesh devices to sleep in between scheduled communications and draw very little power in this state. motes are only active in time slots where they are scheduled to transmit or receive, typically resulting in a duty cycle of < 1%. the optimization soft - ware in the network manager coordinates this schedule automatically. when combined with the eterna low power radio, every mote in a smartmesh networkeven busy routing onescan run on batteries for years. by default, all motes in a network are capable of routing traffic from other motes, which simplifies installation by avoiding the complexity of having distinct routers vs non-routing end nodes. motes may be configured as non-routing to further reduce that particular motes power consumption and to support a wide variety of network topologies. a smartmesh network consists of a self - forming multi - hop mesh of nodes, known as motes, which collect and relay data, and a network manager that monitors and manages network performance and security, and exchanges data with a host application. smartmesh networks communicate using a time slotted channel hopping ?( tsch) link layer, pioneered by dust networks. in a tsch network, all motes in the network are synchronized to within less than a millisecond. time in the network is organized into time slots, which enables collision - free packet exchange and per - transmission channel-hopping. in a smartmesh network, every device has one or more parents ( e.g. mote 3 has motes 1 and 2 as parents) that provide redundant paths to overcome communications interruption due to interference, physical obstruction or multi-path fading. if a packet transmission fails on one path, the next retransmission may try on a different path and different rf channel. a network begins to form when the network manager instructs its on - board access point ( ap) radio to begin sending ? advertisements packets that contain information that enables a device to synchronize to the network and request to join. this message exchange is part of the ? secu - rity ? handshake that establishes encrypted communications between the manager or application, and mote. once motes have joined the network, they maintain synchronization through time corrections when a packet is acknowledged . at the heart of smartmesh motes and network manag - ers is the eterna ieee 802.15.4 e system-on-chip ( soc), featuring dust networks highly integrated, low power radio design, plus an arm cortex-m 3 32- bit micropro - cessor running smartmesh networking software. the smartmesh networking software comes fully compiled yet is configurable via a rich set of application program - ming interfaces ( apis) which allows a host application to interact with the network, e.g. to transfer information to a device, to configure data publishing rates on one or more motes, or to monitor network state or performance metrics. data publishing can be uniform or different for each device, with motes being able to publish infrequently or faster than once per second as needed. an ongoing discovery process ensures that the network continually discovers new paths as the rf conditions change. in addition, each mote in the network tracks per - formance statistics ( e.g. quality of used paths, and lists of potential paths) and periodically sends that information to the network manager in packets called health reports . all nodes are routers. they can transmit and receive. this new node can join anywhere because all nodes can route. sno 02 host application ap sno 01 network manager mote 2 mote 1 mote 3 downloaded from: http:/// ltp 5901- ipm / ltp 5902- ipm 4 59012ipmfa for more information www.linear.com/ltp5901-ipm or www.linear.com/ltp5902-ipm absolute maximum ratings supply voltage on vsupply .................................. 4.20 v input voltage on ai _ 0/1/2/3 inputs ........................ 1.98 v voltage on any digital i/o pin .................................... C0.3 v to vsupply + 0.3 v input rf level .................................................... +10 dbm storage temperature range ( note 3) ..... C55 c to 105 c operating temperature range ltp 5901 i / lpt 5902 i ............................. C40 c to 85 c caution: this part is sensitive to electrostatic discharge (esd). it is very important that proper esd precautions be observed when handling the lt p 5901-ipm / lt p 5902-ipm . pin functions shown in italics are currently not supported in software . pin configuration 12 3 4 5 6 7 8 9 1011 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 gnd reserved nc gpio17gpio18 gpio19 ai_2ai_1 ai_3 ai_0 gnd reserved ncnc resetn tdi tdo tms tck gnd dp4 (gpio23) reserved reserved reserved dp3 (gpio22) / timer8_in dp2 (gpio21) / lptimer_in sleepn / gpio14 dp0 (gpio0) / spim_ss_2n nc gnd 6665 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 gndnc radio_inhibit / gpio15 timen / gpio1 uart_tx uart_tx_ctsn uart_tx_rtsn uart_rx uart_rx_ctsn uart_rx_rtsn gnd vsupply reserved nc nc flash_p_enn / gpio2 spis_ssn / sda spis_sck / scl spis_mosi / gpio26 / uartc1_rx spis_miso / 1_wire / uartc1_tx pwm0 / gpio16 dp1 (gpio20) / timer16_in spim_ss_0n / gpio12 spim_ss_1n / gpio13 gndspim_sck / gpio9 spim_mosi / gpio10 ipcs_ssn / gpio3spim_miso / gpio11 gnd 3132 33 34 35 36 uartc0_tx uartc0_rx ipcs_miso / gpio6 gnd ipcs_mosi / gpio5 ipcs_sck / gpio4 pc package 66-lead pcb (note 1) downloaded from: http:/// ltp 5901- ipm / ltp 5902- ipm 5 59012ipmfa for more information www.linear.com/ltp5901-ipm or www.linear.com/ltp5902-ipm order information lead free finish? part marking* package description temperature range lt p 5901ipc-ipma#pbf lt p 5901ipc-ipma#pbf 66-lead (42mm 24mm 5.5mm) pcb with chip antenna C40c to 85c lt p 5902ipc-ipma#pbf lt p 5902ipc-ipma#pbf 66-lead (37.5mm 24mm 5.5mm) pcb with mmcx connector C40c to 85c ?this product ships with the flash erased at the time of order. oems will need to program devices during development and manufacturing. for legacy part numbers and ordering information go to: http://www.linear.com/product/ lt p 5901-ipm#orderinfo or http://www.linear.com/product/ lt p 5902-ipm#orderinfo *the temperature grade is identified by a label on the shipping container. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ recommended operating conditions the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c and vsupply = 3.6v unless otherwise noted. symbol parameter conditions min typ max units vsupply supply voltage including noise and load regulation l 2.1 3.76 v supply noise 50hz to 2mhz l 250 mv operating relative humidity non-condensing l 10 90 % rh temperature ramp rate while operating in network l C8 +8 c/min dc characteristics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c and vsupply = 3.6v unless otherwise noted. operation/state conditions min typ max units power-on reset during power-on reset, maximum 750s + vsupply rise time from 1v to 1.9v 12 ma doze ram on, arm cortex-m3, flash, radio, and peripherals off, all data and state retained, 32.768khz reference active 1.2 a deep sleep ram on, arm cortex-m3, flash, radio, and peripherals off, all data and state retained, 32.768khz reference inactive 0.8 a in-circuit programming resetn and flash_p_enn asserted, ipcs_sck at 8mhz 20 ma peak operating current +8 dbm +0 dbm system operating at 14.7mhz, radio transmitting, during flash write. maximum duration 4.33 ms. 30 26 ma ma active arm cortex m3, ram and flash operating, radio and all other peripherals off. clock frequency of cpu and peripherals set to 7.3728mhz, vcore = 1.2v 1.3 ma flash write single bank flash write 3.7 ma flash erase single bank page or mass erase 2.5 ma radio tx +0 dbm +8 dbm current with autonomous mac managing radio operation, cpu inactive. clock frequency of cpu and peripherals set to 7.3728mhz. 5.4 9.7 ma ma radio rx current with autonomous mac managing radio operation, cpu inactive. clock frequency of cpu and peripherals set to 7.3728mhz. 4.5 ma downloaded from: http:/// ltp 5901- ipm / ltp 5902- ipm 6 59012ipmfa for more information www.linear.com/ltp5901-ipm or www.linear.com/ltp5902-ipm radio receiver characteristics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c and vsupply = 3.6v unless otherwise noted. parameter conditions min typ max units receiver sensitivity packet error rate (per) = 1% (note 5) C93 dbm receiver sensitivity per = 50% C95 dbm saturation maximum input level the receiver will properly receive packets 0 dbm adjacent channel rejection (high side) desired signal at C82dbm, adjacent modulated channel 5mhz above the desired signal, per = 1% (note 5) 22 dbc adjacent channel rejection (low side) desired signal at C82dbm, adjacent modulated channel 5mhz below the desired signal, per = 1% (note 5) 19 dbc alternate channel rejection (high side) desired signal at C82dbm, alternate modulated channel 10mhz above the desired signal, per = 1% (note 5) 40 dbc alternate channel rejection (low side) desired signal at C82dbm, alternate modulated channel 10mhz below the desired signal, per = 1% (note 5) 36 dbc second alternate channel rejection desired signal at C82dbm, second alternate modulated channel either 15mhz above or below, per = 1% (note 5) 42 dbc co-channel rejection desired signal at C82dbm, undesired signal is an 802.15.4 modulated signal at the same frequency, per = 1% C6 dbc lo feed through C55 dbm frequency error tolerance (note 6) 50 ppm symbol error tolerance 50 ppm received signal strength indicator (rssi) input range C90 to C10 dbm rssi accuracy 6 db rssi resolution 1 db radio specifications the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c and vsupply = 3.6v unless otherwise noted. parameter conditions min typ max units frequency band l 2.4000 2.4835 ghz number of channels l 15 channel separation l 5 mhz channel center frequency where k = 11 to 25, as defined by ieee 802.15.4 l 2405 + 5 ? (k-11) mhz modulation ieee 802.15.4 direct sequence spread spectrum (dsss) raw data rate l 250 kbps antenna pin esd protection hbm per jedec jesd22-a114f (note 2) 6000 v range (note 4) indoor outdoor free space 25c, 50% rh, +2dbi omni-directional antenna, antenna 2m above ground 100 300 1200 m m m downloaded from: http:/// ltp 5901- ipm / ltp 5902- ipm 7 59012ipmfa for more information www.linear.com/ltp5901-ipm or www.linear.com/ltp5902-ipm radio transmitter characteristics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c and vsupply = 3.6v unless otherwise noted. parameter conditions min typ max units output power high calibrated setting low calibrated setting delivered to a 50 load 8 0 dbm dbm spurious emissions 30 mhz to 1000mhz 1 ghz to 12.75ghz 2.4 ghz ism upper band edge (peak) 2.4 ghz ism upper band edge (average) 2.4 ghz ism lower band edge conducted measurement with a 50 single-ended load, +8dbm output power. all measurements made with max hold. r bw = 120khz, v bw = 100hz r bw = 1mhz, v bw = 3mhz r bw = 1mhz, v bw = 3mhz r bw = 1mhz, v bw = 10hz r bw = 100khz, v bw = 100khz ltp 5901- ipm / ltp 5902- ipm 9 59012ipmfa for more information www.linear.com/ltp5901-ipm or www.linear.com/ltp5902-ipm uart ac characteristics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c and vsupply = 3.6v unless otherwise noted. (note 13) symbol parameter conditions min typ max units permitted r x baud rate error both application programming interface (api) and command line interface (cli) uarts l C2 2 % generated t x baud rate error both api and cli uarts l C1 1 % t rx_rts to rx_cts assertion of uart_rx_rtsn to assertion of uart_rx_ctsn, or negation of uart_ rx_rtsn to negation of uart_rx_ctsn l 0 2 ms t rx_cts to rx assertion of uart_rx_ctsn to start of byte l 0 20 ms t eop to rx_ rts end of packet (end of the last stop bit) to negation of uart_rx_rtsn l 0 22 ms t beg_tx_rts to tx_cts assertion of uart_tx_rtsn to assertion of uart_tx_ctsn l 0 22 ms t end_tx_cts to tx_ rts negation of uart_tx_ctsn to negation of uart_tx_rtsn 2 bit period t tx_cts to tx assertion of uart_tx_ctsn to start of byte l 0 2 bit period t eop to tx_ rts end of packet (end of the last stop bit) to negation of uart_tx_rtsn l 0 1 bit period t rx_interbyte receive inter-byte delay l 100 ms t rx_interpacket receive inter-packet delay l 20 ms t tx_interpacket transmit inter-packet delay l 1 bit period t tx to tx_cts start of byte to negation of uart_tx_ctsn l 0 ns 59012ipm f01 uart_rx_rtsn uart_rx_ctsn t rx_rts to rx_cts uart_rx uart_tx_rtsn uart_tx_ctsn uart_tx t eop to rx_rts t rx_rts to rx_cts t rx_cts to rx t rx_interbyte byte 0 byte 1 byte 0 byte 1 t beg_tx_rts to tx_cts t end_tx_cts to tx_rts t tx_cts to tx t tx to tx_cts t eop to tx_rts t end_tx_rts to tx_cts figure 1. api uart timing downloaded from: http:/// ltp 5901- ipm / ltp 5902- ipm 10 59012ipmfa for more information www.linear.com/ltp5901-ipm or www.linear.com/ltp5902-ipm time n ac characteristics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c and vsupply = 3.6v unless otherwise noted. (note 13) symbol parameter conditions min typ max units t strobe timen signal strobe width l 125 s t response delay from rising edge of timen to the start of time packet on api uart l 0 100 ms t time_hold delay from end of time packet on api uart to falling edge of subsequent timen l 0 ns timestamp resolution (note 10) l 1 s network-wide time accuracy (note 11) l 5 s 59012ipm f02 timen uart_tx t strobe t time_hold t response time indication payload figure 2. timestamp timing radio _ inhibit ac characteristics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c and vsupply = 3.6v unless otherwise noted. (note 13) symbol parameter conditions min typ max units t radio_off delay from rising edge of radio_inhibit to radio disabled l 20 ms t radio_inhibit_strobe maximum radio_inhibit strobe width l 2 s 59012ipm f03 radio_inhibit radio state t radio_off t radio_inhibit_strobe active/off active/off off figure 3. radio_inhibit timing downloaded from: http:/// ltp 5901- ipm / ltp 5902- ipm 11 59012ipmfa for more information www.linear.com/ltp5901-ipm or www.linear.com/ltp5902-ipm flash ac characteristics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c and vsupply = 3.6v unless otherwise noted. (note 13) symbol parameter conditions min typ max units t write time to write a 32-bit word (note 12) l 21 s t page_erase time to erase a 2kb page (note 12) l 21 ms t mass_erase time to erase 256kb flash bank (note 12) l 21 ms data retention 25c 85c 105c 100 20 8 years y ears years flash spi slave ac characteristics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c and vsupply = 3.6v unless otherwise noted. (note 13) symbol parameter conditions min typ max units t fp_en_to_reset setup from assertion of flash_p_enn to assertion of resetn l 0 ns t fp_enter delay from the assertion resetn to the first falling edge of ipcs_ssn l 125 s t fp_exit delay from the completion of the last flash spi slave transaction to the negation of resetn and flash_p_enn l 10 s t sss ipcs_ssn setup to the leading edge of ipcs_sck l 15 ns t ssh ipcs_ssn hold from trailing edge of ipcs_sck l 15 ns t ck ipcs_sck period l 300 ns t dis ipcs_mosi data setup l 15 ns t dih ipcs_mosi data hold l 5 ns t dov ipcs_miso data valid l C5 30 ns t off ipcs_miso data tri-state from trailing edge of ipcs_ssn l 0 30 ns 59012ipm f04 ipcs_sck ipcs_mosi ipcs_ssn resetn flash_p_enn t fp_en_to_reset t fp_enter t sss t ck t ssh t fp_exit t dis t dih figure 4. flash programming interface timing downloaded from: http:/// ltp 5901- ipm / ltp 5902- ipm 12 59012ipmfa for more information www.linear.com/ltp5901-ipm or www.linear.com/ltp5902-ipm spi master ac characteristics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c and vsupply = 3.6v unless otherwise noted. (note 13) symbol parameter conditions min typ max units t sss spim_ssxn setup to the leading edge of spim_sck l t ck-30 ns t ssh spim_ssxn hold from trailing edge of spim_sck l t ck-30 ns t ck spim_sck period l 268 ns t dis spim_mosi data setup l 30 ns t dih spim_mosi data hold l 5 ns t dov spim_miso data valid l C5 30 ns t off spim_miso data tri-state from trailing edge of spim_ssxn l 0 30 ns figure 5. spi master timing - cpha = 0 figure 6. spi master timing - cpha = 1 59012ipm f05 spim_misospim_mosi spim_ssxn t sss t ck t ssh spim_sck cpol = 1 cpol = 0 t dih t dis t dov t off 59012ipm f06 spim_misospim_mosi spim_ssxn t sss t ck t ssh spim_sck cpol = 1 cpol = 0 t dih t off t dis t dov downloaded from: http:/// ltp 5901- ipm / ltp 5902- ipm 13 59012ipmfa for more information www.linear.com/ltp5901-ipm or www.linear.com/ltp5902-ipm i 2 c ac characteristics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c and vsupply = 3.6v unless otherwise noted. (note 13) symbol parameter conditions min typ max units f scl scl frequency 184khz operation 92khz operation l 184.3 92.2 188 94 khz khz t hd_ sta start hold time (scl from sda) 184khz operation 92khz operation l 1 2 s s t su_ sta setup time for a repeated start 184khz operation, 750ns scl rise time 92khz operation, 1.5s scl rise time l 300 600 ns ns t hd_ dat data hold time 184khz operation 92khz operation l 1 2 s s t su_ dat data setup time 184khz operation 92khz operation l 1 2 s s t su_sto setup time for stop condition 184khz operation 92khz operation l 1 2 s s 1-wire master the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c and vsupply = 3.6v unless otherwise noted. (note 13) symbol parameter conditions min typ max units t rstl reset low l 527 556 584 s t ps presence sample l 60.1 69.4 79 s t bit_period 1_wire data bit period l 82 86.8 92 s t low0 1_wire write data 0 low width l 65 69 82 s t low1 1_wire write data 1 low width l 8.2 8.7 9.2 s t lowr 1_wire read data low width l 8.2 8.7 9.2 s t rs read sample from 1_wire low l 13.2 14.6 15.0 s figure 7. i 2 c master timing 59012ipm f07 scl sda t hd_sta t su_sta t hd_sta t hd_dat t su_dat t hd_dat downloaded from: http:/// ltp 5901- ipm / ltp 5902- ipm 14 59012ipmfa for more information www.linear.com/ltp5901-ipm or www.linear.com/ltp5902-ipm note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: esd (electrostatic discharge) sensitive device. esd protection devices are used extensively internal to eterna. however, high electrostatic discharge can damage or degrade the device. use proper esd handling precautions. note 3: extended storage at high temperature is discouraged, as this negatively affects the data retention of eternas calibration data. see the flash data retention section for details. note 4: actual rf range is subject to a number of installation-specific variables including, but not restricted to ambient temperature, relative humidity, presence of active interference sources, line-of-sight obstacles, and near-presence of objects (for example, trees, walls, signage, and so on) that may induce multipath fading. as a result, range varies. note 5: as specified by ieee std. 802.15.4-2006: wireless medium access control (mac) and physical layer (phy) specifications for low- rate wireless personal area networks (lr-wpans) http://standards.ieee. org/findstds/standard/802.15.4-2011.html . note 6: ieee std. 802.15.4-2006 requires transmitters to maintain a frequency tolerance of better than 40 ppm.note 7: per-pin i/o types are provided in the pin functions section. note 8: vih maximum voltage input must respect the vsupply maximum voltage specification.note 9: the analog inputs to the adc can be modeled as a series resistor to a capacitor. at a minimum the entire circuit, including the source impedance for the signal driving the analog input should be designed to settle to within ? lsb within the sampling window to match the performance of the adc. note 10: see the smartmesh ip mote api guide for the time indication notification definition.note 11: network time accuracy is a statistical measure and varies over the temperature range, reporting rate and the location of the device relative to the manager in the network. see the typical performance characteristics section for a more detailed description. note 12: code execution from flash banks being written or erased is suspended until completion of the flash operation.note 13: guaranteed by design. not production tested. figure 8. 1-wire master timing flash spi slave ac characteristics t bit_period t low1 t lowr t rstl t ps t bit_period t low0 t bit_period t rs 59012ipm f08 1-wire 1-wire1-wire 1-wire downloaded from: http:/// ltp 5901- ipm / ltp 5902- ipm 15 59012ipmfa for more information www.linear.com/ltp5901-ipm or www.linear.com/ltp5902-ipm network motes typically route through at least two parents the traffic destined for the manager. the supply current graphs shown in figure 9 include a parameter called de - scendants. in these graphs the term descendants is short for traffic-weighted descendants and refers to an amount of activity equivalent to the number of descendants if all of the network traffic directed to the mote in question. generally the number of descendants of a parent is more, typically 2 x or more, than the number of traffic-weighted descendants. for example, with reference to figure 10. network graph mote p1 has 0.75 traffic-weighted de - scendants. to obtain this value notice that mote d1 routes half its packets through mote p1 adding 0.5 to the traffic- weighted descendant value; the other half of d1s traffic is routed through its other parent, p2. mote d2 routes half its packets through mote d 1 ( the other half going through parent p3), which we know routes half its packets to mote p 1, adding another 0.25 to the traffic - weighted descendant value for a total traffic-weighted descendant value of 0.75. as described in the application time synchronization section, eterna provides two mechanisms for applications to maintain a time base across a network. the synchro- nization performance plots that follow were generated using the more precise timen input. publishing rate is the rate a mote application sends upstream data. syn - chronization improves as the publishing rate increases. baseline synchronization performance is provided for a network operating with a publishing rate of zero. actual performance for applications in network will improve as publishing rates increase. all synchronization testing was performed with the 1- hop mote inside a temperature chamber. timing errors due to temperature changes and temperature differences both between the manager and this mote and between this mote and its descendents therefore propagated down through the network. the syn - chronization of the 3- hop and 5- hop motes to the manager was then affected by the temperature ramps even though they were at room temperature. for 2 c/minute testing the temperature chamber was cycled between C40 c and 85c at this rate for 24 hours. for 8 c/minute testing, the temperature chamber was rapidly cycled between 85 c and 45c for 8 hours, followed by rapid cycling between C5 c and 45 c for 8 hours, and lastly, rapid cycling between C40c and 15c for 8 hours. figure 10. example network graph reporting interval (sec) 0 0 median latency (sec) 1.0 1.5 2.0 4.0 58012ipm f09b 0.5 3.0 3.52.5 30 10 20 5 hops4 hops 3 hops 2 hops 1 hop reporting interval (sec) 0 0 supply current (a) 100 58012ipm f09c 200 30 10 20 5 descendants2 descendants 1 descendants 0 descendants figure 9 temperature (c) C60 0 supply current (a) 20 60 80 100 120 140 58012ipm f09a 40 C10 40 90 2 descendants 5sec reporting5 descendants 30sec reporting 2 descendants 30sec reporting 0 descendants 5sec reporting 0 descendants 30sec reporting manager 1 hop2 hop 3 hop 58012ipm f10 p1 p2 p3 d1 d2 typical performance characteristics downloaded from: http:/// ltp 5901- ipm / ltp 5902- ipm 16 59012ipmfa for more information www.linear.com/ltp5901-ipm or www.linear.com/ltp5902-ipm typical performance characteristics timen synchronization error 0 packet/s publishing rate, 1 hop, room temperature timen synchronization error 0 packet/s publishing rate, 3 hops, room temperature timen synchronization error 0 packet/s publishing rate, 5 hops, room temperature timen synchronization error 0 packet/s publishing rate, 1 hop, 2c/min timen synchronization error 0 packet/s publishing rate, 3 hops, 2c/min timen synchronization error 0 packet/s publishing rate, 5 hops, 2c/min timen synchronization error 0 packet/s publishing rate, 1 hop, 8c/min timen synchronization error 0 packet/s publishing rate, 3 hops, 8c/min timen synchronization error 0 packet/s publishing rate, 5 hops, 8c/min synchronization error (s) C40 0 normalized frequency of occurrence (%) 10 30 40 50 60 C30 58012ipm g01 20 40 C20 0 10 20 30 C10 = 0.0 = 0.9 n = 89700 synchronization error (s) C40 0 normalized frequency of occurrence (%) 5 15 20 25 30 C30 58012ipm g02 10 40 C20 0 10 20 30 C10 = C 0.2 = 1.7 n = 89699 synchronization error (s) C40 0 normalized frequency of occurrence (%) 2 6 8 10 12 14 C30 58012ipm g03 4 40 C20 0 10 20 30 C10 = C 0.2 = 3.6 n = 89698 synchronization error (s) C40 0 normalized frequency of occurrence (%) 5 10 15 20 C30 58012ipm g04 40 C20 0 10 20 30 C10 = 1.5 = 3.3 n = 93812 synchronization error (s) C40 0 normalized frequency of occurrence (%) 2 4 6 8 10 12 14 C30 58012ipm g05 40 C20 0 10 20 30 C10 = 0.9 = 3.9 n = 93846 synchronization error (s) C40 0 normalized frequency of occurrence (%) 2 4 6 8 10 12 C30 58012ipm g07 40 C20 0 10 20 30 C10 = 3.6 = 5.0 n = 88144 synchronization error (s) C40 0 normalized frequency of occurrence (%) 2 4 6 8 10 14 12 C30 58012ipm g08 40 C20 0 10 20 30 C10 = 1.1 = 3.8 n = 88179 synchronization error (s) C40 0 normalized frequency of occurrence (%) 1 2 3 4 5 7 6 C30 58012ipm g09 40 C20 0 10 20 30 C10 = 1.0 = 7.4 n = 88178 synchronization error (s) C40 0 normalized frequency of occurrence (%) 1 2 3 4 5 6 7 C30 58012ipm g06 40 C20 0 10 20 30 C10 = 1.0 = 7.7 n = 93845 downloaded from: http:/// ltp 5901- ipm / ltp 5902- ipm 17 59012ipmfa for more information www.linear.com/ltp5901-ipm or www.linear.com/ltp5902-ipm typical performance characteristics timen synchronization error 1 packet/s publishing rate, 1 hop, room temperature timen synchronization error 1 packet/s publishing rate, 3 hops, room temperature timen synchronization error 1 packet/s publishing rate, 5 hops, room temperature timen synchronization error 1 packet/s publishing rate, 1 hop, 2c/min timen synchronization error 1 packet/s publishing rate, 3 hops, 2c/min timen synchronization error 1 packet/s publishing rate, 5 hops, 2c/min timen synchronization error 1 packet/s publishing rate, 1 hop, 8c/min timen synchronization error 1 packet/s publishing rate, 3 hops, 8c/min timen synchronization error 1 packet/s publishing rate, 5 hops, 8c/min synchronization error (s) C40 0 normalized frequency of occurrence (%) 10 20 30 40 60 50 C30 58012ipm g10 40 C20 0 10 20 30 C10 = 0.0 = 1.2 n = 22753 synchronization error (s) C40 0 normalized frequency of occurrence (%) 10 20 30 40 60 50 C30 58012ipm g11 40 C20 0 10 20 30 C10 = C0.2 = 1.2 n = 17008 synchronization error (s) C40 0 normalized frequency of occurrence (%) 10 20 30 40 50 C30 58012ipm g12 40 C20 0 10 20 30 C10 = C0.2 = 1.2 n = 17007 synchronization error (s) C40 0 normalized frequency of occurrence (%) 10 5 15 20 35 3025 C30 58012ipm g13 40 C20 0 10 20 30 C10 = 0.5 = 1.9 n = 85860 synchronization error (s) C40 0 normalized frequency of occurrence (%) 10 5 15 20 45 35 4030 25 C30 58012ipm g14 40 C20 0 10 20 30 C10 = 0.1 = 1.5 n = 85858 synchronization error (s) C40 0 normalized frequency of occurrence (%) 10 5 15 20 35 3025 C30 58012ipm g15 40 C20 0 10 20 30 C10 = 0.1 = 1.5 n = 85855 synchronization error (s) C40 0 normalized frequency of occurrence (%) 10 20 30 60 5040 C30 58012ipm g16 40 C20 0 10 20 30 C10 = 0.2 = 1.4 n = 33932 synchronization error (s) C40 0 normalized frequency of occurrence (%) 10 20 30 60 5040 C30 58012ipm g17 40 C20 0 10 20 30 C10 = 0.0 = 1.3 n = 33930 synchronization error (s) C40 0 normalized frequency of occurrence (%) 10 20 30 50 40 C30 58012ipm g18 40 C20 0 10 20 30 C10 = C1.0 = 1.3 n = 33929 downloaded from: http:/// ltp 5901- ipm / ltp 5902- ipm 18 59012ipmfa for more information www.linear.com/ltp5901-ipm or www.linear.com/ltp5902-ipm typical performance characteristics as described in the smartmesh network overview sec- tion, devices in network spend the vast majority of their time inactive in their lowest power state ( doze). on a synchronous schedule a mote will wake to communicate with another mote. regularly occurring sequences which wake, perform a significant function and return to sleep are considered atomic. these operations are considered atomic as the sequence of events can not be separated into smaller events while performing a useful function. for example, transmission of a packet over the radio is an atomic operation. atomic operations may be characterized in either charge or energy. in a time slot where a mote successfully sends a packet, an atomic transmit includes setup prior to sending the message, sending the message, receiving the acknowledgment and the post processing needed as a result of the message being sent. similarly in a time slot when a mote successfully receives a packet, an atomic receive includes setup prior to listening, listening until the start of the packet transition, receiving the packet, sending the acknowledge and the post processing required due to the arrival of the packet.to ensure reliability each mote in the network is provided multiple time slots for each packet it nominally will send and forward. the time slots are assigned to communicate upstream with at least two different motes. when combined with frequency hopping this provides temporal, spacial and spectral redundancy. given this approach a mote will often listen for a message that it will never receive, since the time slot is not being used by the transmitting mote. it has already successfully transmitted the packet. since typically 3 time slots are scheduled for every 1 packet to be sent or forwarded, motes will perform more of these atomic idle listens than atomic transmit or atomic receive sequences. examples of transmit, receive and idle listen atomic operations are shown in figure 11. downloaded from: http:/// ltp 5901- ipm / ltp 5902- ipm 19 59012ipmfa for more information www.linear.com/ltp5901-ipm or www.linear.com/ltp5902-ipm typical performance characteristics figure 11 downloaded from: http:/// ltp 5901- ipm / ltp 5902- ipm 20 59012ipmfa for more information www.linear.com/ltp5901-ipm or www.linear.com/ltp5902-ipm pin functions the following table organizes the pins by functional groups. for those i/o with multiple functions the alternate functions are shown on the second and third line in their respective row. the no column provides the pin number . the second column lists the function. the type column lists the i/o type. the i/o column lists the direction of the signal relative to eterna. the pull column shows which signals have a fixed passive pull-up or pull-down. the description column provides a brief signal description. no power supply type i/o pull description 1 gnd power - - ground connection 11 gnd power - - ground connection 20 gnd power - - ground connection 30 gnd power - - ground connection 34 gnd power - - ground connection 37 gnd power - - ground connection 42 gnd power - - ground connection 56 gnd power - - ground connection 66 gnd power - - ground connection 55 vsupply power - - power supply input to eterna no radio type i/o pull description 64 radio_inhibit 1 (note 14) i - radio inhibit 4 gpio17 1 i/o - general purpose digital i/o 5 gpio18 1 i/o - general purpose digital i/o 6 gpio19 1 i/o - general purpose digital i/o - antenna n/a n/a - chip antenna ( lt p 5901) or mmcx connector ( lpt 5902) no analog type i/o pull description 7 ai_2 analog i - analog input 2 8 ai_1 analog i - analog input 1 9 ai_3 analog i - analog input 3 10 ai_0 analog i - analog input 0 no reset type i/o pull description 15 resetn 1 i up reset input, active low no jtag type i/o pull description 16 tdi 1 i up jtag test data in 17 tdo 1 o - jtag test data out 18 tms 1 i up jtag test mode select 19 tck 1 i down jtag test clock pin functions shown in italics are currently not supported in software. downloaded from: http:/// ltp 5901- ipm / ltp 5902- ipm 21 59012ipmfa for more information www.linear.com/ltp5901-ipm or www.linear.com/ltp5902-ipm pin functions pin functions shown in italics are currently not supported in software. no gpios type i/o pull description 21 dp4 (gpio23) 1 i/o - general purpose digital i/o 25 dp3 (gpio22) timer8_ext 1 i/o i - - general purpose digital i/o external input to 8-bit t imer/counter 26 dp2 (gpio21) lptimer_ext 1 i/o i - - general purpose digital i/o external input to low power timer/counter 28 dp0 (gpio0) spim_ss_2n 1 i/o o - - general purpose digital i/o spi master slave select 2, active low 45 dp1 (gpio20) timer16_ext 1 i/o i - - general purpose digital i/o external input to 16-bit timer/counter no special purpose type i/o pull description 27 sleepn 1 (note 14) i - deep sleep, active low 46 pwm0 timer16_out gpio16 2 o o i/o - - - pulse width modulator 0 16-bit timer/counter match output/pwm output general purpose digital i/o 63 timen 1 (note 14) i - time capture request, active low no cli type i/o pull description 31 uartc0_tx 2 o - cli uart 0 transmit 32 uartc0_rx 1 i up cli uart 0 receive no spi master type i/o pull description 38 spim_miso gpio11 1 i i/o - - spi master (miso) master in slave out port general purpose digital i/o 40 spim_mosi gpio10 2 o i/o - - spi master (mosi) master out slave in port general purpose digital i/o 41 spim_sck gpio9 2 o i/o - - spi master (sck) serial clock port general purpose digital i/o 43 spim_ss_1n gpio13 1 o i/o - - spi master slave select 1, active low general purpose digital i/o 44 spim_ss_0n gpio12 1 o i/o - - spi master slave select 0, active low general purpose digital i/o downloaded from: http:/// ltp 5901- ipm / ltp 5902- ipm 22 59012ipmfa for more information www.linear.com/ltp5901-ipm or www.linear.com/ltp5902-ipm no ipcs spi/flash programming (note 15) type i/o pull description 33 ipcs_miso timer16_out gpio6 2 i o i/o - - - spi flash emulation (miso) master in slave out port 16-bit timer/counter match output/pwm output general purpose digital i/o 35 ipcs_mosi timer16_ext gpio5 1 i i i/o - - - spi flash emulation (mosi) master out slave in port external input to 16-bit timer/counter general purpose digital i/o 36 ipcs_sck timer8_ext gpio4 1 i i i/o - - - spi flash emulation (sck) serial clock port external input to 8-bit t imer/counter general purpose digital i/o 39 ipcs_ssn lptimer_ext gpio3 1 i i i/o - - - spi flash emulation slave select, active low external input to low power timer/counter general purpose digital i/o 51 flash_p_enn 1 i up flash program enable, active low pin functions pin functions shown in italics are currently not supported in software. no i 2 c/1-wire/spi slave type i/o pull description 47 spis_miso uartc1_tx 1_wire 2 o o i/o - - - spi slave (miso) master in slave out port cli uar t 1 transmit 1 wire master 48 spis_mosi uartc1_rx gpio26 1 i i i/o - - - spi slave (mosi) master out slave in port cli uar t 1 receive general purpose digital i/o 49 spis_sck scl 2 i i/o - - spi slave (sck) serial clock port i 2 c serial clock 50 spis_ssn sda 2 i i/o - - spi slave select, active low i 2 c serial data no api uart type i/o pull description 57 uart_rx_rtsn 1 (note 14) i - uart receive ( rts ) request to send, active low 58 uart_rx_ctsn 1 o - uart receive (cts) clear to send, active low 59 uart_rx 1 (note 14) i - uart receive 60 uart_tx_rtsn 1 o - uart transmit ( rts ) request to send, active low 61 uart_tx_ctsn 1 (note 14) i - uart transmit (cts) clear to send, active low 62 uart_tx 2 o - uart transmit note 14: these inputs are always enabled and must be driven or pulled to a valid state to avoid leakage. note 15: embedded programming over the ipcs spi bus is only avaliable when resetn is asserted. downloaded from: http:/// ltp 5901- ipm / ltp 5902- ipm 23 59012ipmfa for more information www.linear.com/ltp5901-ipm or www.linear.com/ltp5902-ipm pin functions vsupply: system and i/o power supply. provides power to the module. the digital-interface i/o voltages are also set by this voltage.antenna: multiplexed receiver input and transmitter output pin. the impedance presented to the mmcx con - nector should be 50, single - ended with respect to ground . ai_0, ai_1, ai_2, ai_3: analog inputs. these pins are multiplexed to the analog input chain. the analog input chain, as shown in figure 12, is software-configurable and includes a variable-gain amplifier, an offset-dac for adjusting input range, and a 10- bit adc. valid input range is between 0 v to 1.8 v. analog inputs can be sampled as described in section signal/data acquisition and control. uart _ rx, uart _ rx _ rtsn, uart _ rx _ ctsn, uart _ tx , uart _ tx _ rtsn, uart _ tx _ ctsn : the api uart interface includes bidirectional wake up and flow control. unused input signals must be driven or pulled to their inactive state . timen: strobing the timen input is the most accurate method to acquire the network time maintained by eterna. eterna latches the network time stamp with sub-micro - second resolution on the rising edge of the timen signal and produces a packet on the api serial port containing the timing information.uartc0_rx, uartc0_tx: the cli uart provides a mechanism for monitoring, configuration and control of eterna during operation. for a complete description of the supported commands see the smartmesh ip mote cli guide . gpio0, gpio3 to gpio6, gpio9 to gpio13, gpio16, gpio20 to gpio23, gpio26: general purpose i/os that can be sampled or driven as described in the on-chip software development kit (on-chip sdk) . flash _p_ enn, ipcs _ ssn, ipcs _ sck, ipcs _ miso , ipcs_ssn: the in-circuit programming control system ( ipcs) bus enables in - circuit programming of eterna s flash memory. ipcs_sck is a clock and should be terminated appropriately for the driving source to prevent overshoot and ringing. spim_clk, spim_miso, spim_mosi, spim_ss_0n, spim_ss_1n, spim_ss_4n: the spi master bus with support for up to three spi slave devices, via the on-chip software development kit ( on-chip sdk) provides an interface to spi peripheral slave devices . the spi interface is synchronous to spim_clk, which should be treated as a clock signal and terminated appropriately .1-wire: the 1- wire master clock/data/power signal . see the on-chip software development kit ( on-chip sdk) for details on operating the 1-wire master controller. scl, sda: the i 2 c bus scl and sda should be externally pulled to v supply with a 10 k resistor. see the on-chip software development kit ( on-chip sdk) for details on operating the 1-wire master controller. figure 12. analog input chain 59012ipm f12 analog input 3-bitvga + 4-bit dac 10-bit adc resetn : the asynchronous reset signal is internally pulled up. resetting eterna will result in the arm cortex m3 rebooting and loss of network connectivity. use of this signal for resetting eterna is not recommended, except during power-on and in-circuit programming. radio_inhibit: radio_inhibit provides a mechanism for an external device to temporarily disable radio operation . failure to observe the timing requirements defined in the radio_inhibit ac characteristics section, may result in unreliable network operation. in designs where the radio_inhibit function is not needed the input must either be tied, pulled or actively driven low to avoid excess leakage. tms, tck, tdi, tdo: jtag port supporting software debug and boundary scan. sleepn: the sleepn function is not currently supported in software. the sleepn input must either be tied, pulled or actively driven high to avoid excess leakage. downloaded from: http:/// ltp 5901- ipm / ltp 5902- ipm 24 59012ipmfa for more information www.linear.com/ltp5901-ipm or www.linear.com/ltp5902-ipm figure 13. eterna block diagram 4-bit dac vga bpf ppf agc lpf adc dac pll rssi lna pa 20mhz 32khz 32khz, 20mhz ptat 59012ipm f13 bat load limiter voltage reference analog core digital core core regulator clock regulator analog regulator pa dc/dc converter primary dc/dc converter relaxation oscillator por timers sched sram 72kb flash 512kb flash controller code aes auto mac 802.15.4 mod 802.15.4 framing dma ipcs spi slave cli uart (2-pin) api uart (6-pin) adc ctrl 802.15.4 demod system pmu/ clock control 10-bit adc operation the lt p 5901-ipm / lt p 5902-ipm is the world s most energy efficient ieee 802.15.4 compliant platform, enabling bat- tery and energy harvested applications. with a powerful 32-bit arm cortex-m3, best-in-class radio, flash, ram and purpose-built peripherals, eterna provides a flexible, scalable and robust networking solution for applications demanding minimal energy consumption and data reliability in even the most challenging rf environments.shown in figure 13, eterna integrates purpose - built peripherals that excel in both low operating-energy con - sumption and the ability to rapidly and precisely cycle between operating and low-power states. items in the gray shaded region labeled analog core correspond to the analog/rf components. power supply eterna is powered from a single pin, vsupply, which powers the i/o cells and is also used to generate internal supplies. eterna s two on - chip dc / dc converters minimize eternas energy consumption while the device is awake. to conserve power the dc/dc converters are disabled when the device is in low power state. eternas power supply conditioning architecture, including the two integrated dc / dc converters and three integrated low dropout regula - tors, provides excellent rejection of supply noise. eternas operating supply voltage range is high enough to support direct connection to lithium-thionyl chloride ( li-socl 2 ) sources and wide enough to support battery operation over a broad temperature range. downloaded from: http:/// ltp 5901- ipm / ltp 5902- ipm 25 59012ipmfa for more information www.linear.com/ltp5901-ipm or www.linear.com/ltp5902-ipm operation supply monitoring and reset eterna integrates a power-on reset ( por) circuit. as the resetn input pin is nominally configured with an internal pull-up resistor, no connection is required. for a graceful shutdown, the software and the networking layers should be cleanly halted via api commands prior to assertion of the resetn pin. see the smartmesh ip mote api guide for details on the disconnect and reset commands. eterna includes a soft brown-out monitor that fully protects the flash from corruption in the event that power is removed while writing to flash. integrated flash supervisory func - tionality, in conjunction with a fault tolerant file system, yields a robust nonvolatile storage solution.p recision timing a major feature of eterna over competing 802.15.4 prod - uct offerings is its low-power dedicated timing hardware and timing algorithms. this functionality provides timing precision two to three orders of magnitude better than any other low-power solution available at the time of publication. improved timing accuracy allows motes to minimize the amount of radio listening time required to ensure packet reception thereby lowering even further the power consumed by smartmesh networks. eternas patented timing hardware and timing algorithms provide superior performance over rapid temperature changes, further differentiating eternas reliability when compared with other wireless products. in addition, precise timing enables networks to reduce spectral dead time, increasing total network throughput. application time synchronization in addition to coordinating time slots across the network, which is transparent to the user, eternas timing manage - ment is used to support two mechanisms to share network time. having an accurate, shared, network-wide time base enables events to be accurately time stamped or tasks to be performed in a synchronized fashion across a network. eterna will send a time packet through its serial interface when one of the following occurs: n eterna receives an api request to read time n the timen signal is asserted the use of timen has the advantage of being more accu- rate. the value of the timestamp is captured in hardware relative to the rising edge of timen. if an api request is used, due to packet processing, the value of the timestamp may be captured several milliseconds after receipt of the packet due to packet processing. see the timen ac characteristics section for the time functions definition and specifications.time references eterna includes three clock sources: an internal relaxation oscillator , a low power oscillator designed for a 32.768 khz cr ystal, and the radio reference oscillator designed for a 20mhz crystal. relaxation oscillator the relaxation oscillator is the primary clock source for eterna, providing the clock for the cpu, memory subsystems, and all peripherals. the internal relaxation oscillator is dynamically calibrated to 7.3728 mhz. the internal relaxation oscillator typically starts up in a few s, providing an expedient, low energy method for duty cycling between active and low power states. quick start - up from the doze state, defined in the state diagram section, allows eterna to wake up and receive data over the uart and spi interfaces by simply detecting activity on the appropriate signals.32.768khz crystal once eterna is powered up and the 32.768 khz crystal source has begun oscillating, the 32.768 khz crystal re - mains operational while in the active state, and is used as the timing basis when in doze state. see the state diagram section for a description of eternas operational states.20mhz crystal the 20 mhz crystal source provides a frequency reference for the radio, and is automatically enabled and disabled by eterna as needed. downloaded from: http:/// ltp 5901- ipm / ltp 5902- ipm 26 59012ipmfa for more information www.linear.com/ltp5901-ipm or www.linear.com/ltp5902-ipm operation radio eterna includes the lowest power commercially available 2.4ghz ieee 802.15.4 e radio by a substantial margin. ( please refer to the radio specifications section for power consumption numbers.). eternas integrated power amplifier is calibrated and temperature compensated to consistently provide power at a limit suitable for worldwide radio certifications. additionally, eterna uniquely includes a hardware-based autonomous mac that handles precise sequencing of peripherals, including the transmitter, the receiver, and advanced encryption standard ( aes) pe - ripherals. the hardware - based autonomous media access controller ( mac) minimizes cpu activity, thereby further decreasing power consumption. uarts the principal network interface is through the application programming interface ( api) uart. a command-line interface ( cli) is also provided for support of test and debug functions. both uarts sense activity continuously, consuming virtually no power until data is transferred over the port and then automatically returning to their lowest power state after the conclusion of a transfer. the defini - tion for packet encoding on the api uart interface can be found in the smartmesh ip mote api guide and the cli command definitions can be found in the smartmesh ip mote cli guide . api uart protocol the api uart protocol was created with the goal of supporting a wide range of companion multipoint control units ( mcus) while reducing power consumption of the system. the receive half of the api uart protocol includes two additional signals in addition to uart _ rx: uart _ rx _ rtsn and uart_rx_ctsn. the transmit half of the api uart protocol includes two additional signals in addition to uart_tx: uart_tx_rtsn and uart_tx_ctsn. the api uart protocol is referred to as mode 4. in the figures accompanying the protocol descriptions, signals driven by the companion processor are drawn in black and signals driven by eterna are drawn in blue. figure 14. uart mode 4 transmit flow control 59012ipm f14 uart_tx byte 0 byte 1 uart_tx_ctsn uart_tx_rtsn uart mode 4 uart mode 4 incorporates level sensitive flow control on the tx channel and requires no flow control on the rx channel, supporting 115200 baud. the use of level- sensitive flow control signals enables data rates above 9600 baud with the option of using a reduced set of the flow control signals; however, mode 4 has specific limitations . first, the use of the rx flow control signals ( uart _ rx _ rtsn and uart _ rx _ ctsn) for mode 4 are optional provided the use is limited to the industrial temperature range (C40 c to 85 c); otherwise, the flow control is mandatory . if rx flow control signals are not used, uart_rx_rtsn should be tied to vsupply ( inactive) and uart _ rx _ ctsn should be left unconnected . second, unless the companion processor is always ready to receive a packet, the companion processor must negate uart_tx_ctsn prior to the end of the current packet. failure to negate uart _ tx _ ctsn prior to the end of a packet may result in back to back packets. third, the companion processor must wait at least t rx_rts to rx_cts between transmmitting packets on uart_rx. see the uart ac characteristics section for complete timing specifications . packets are hdlc encoded with one stop bit and no parity bit. the flow control signals for the tx channel are shown in figure 14. transfers are initiated by eterna asserting uart _ tx _ rtsn. the uart _ tx _ ctsn signal may be actively driven by the companion processor when ready to receive a packet or uart_tx_ctsn may be tied low if the companion processor is always ready to receive a packet. after detecting a logic 0 on uart_tx_ctsn eterna sends the entire packet. following the transmission of the final byte in the packet eterna negates uart _ tx _ rtsn and waits for t tx _ interpacket , defined in the uart ac characteristics section before asserting uart_tx_rtsn again. downloaded from: http:/// ltp 5901- ipm / ltp 5902- ipm 27 59012ipmfa for more information www.linear.com/ltp5901-ipm or www.linear.com/ltp5902-ipm operation for details on the timing of the uart protocol, see the uart ac characteristics section. cli uart the command line interface ( cli) uart port is a two wire protocol ( tx and rx) that operates at a fixed 9600 baud rate with one stop bit and no parity. the cli uart interface is intended to support command line instructions and response activity.autonomous mac eterna was designed as a system solution to provide a reliable, ultralow power, and secure network. a reliable network capable of dynamically optimizing operation over changing environments requires solutions that are far too complex to completely support through hardware acceleration alone. as described in the precision timing section, proper time management is essential for optimizing a solution that is both low power and reliable. to address these requirements eterna includes the autonomous mac , which incorporates a coprocessor for controlling all of the time critical radio operations. the autonomous mac provides two benefits: first, preventing variable software latency from affecting network timing and second, greatly reducing system power consumption by allowing the cpu to remain inactive during the majority of the radio activity. the autonomous mac, provides software independent timing control of the radio and radio related functions , re sulting in superior reliability and exceptionally low power . security network security is an often overlooked component of a complete network solution. proper implementation of se - curity protocols is significant in terms of both engineering effort and market value in an oem product. eterna system solutions provide a fips-197 validated encryption scheme that includes authentication and encryption at the mac and network layers with separate keys for each mote. this not only yields end-to-end security, but if a mote is somehow compromised, communication from other motes is still secure. a mechanism for secure key exchange al - lows keys to be kept fresh. to prevent physical attacks, eterna includes hardware support for electronically locking devices, thereby preventing access to eternas flash and ram memory and thus the keys and code stored therein. temperature sensor eterna includes a calibrated temperature sensor on chip. the temperature readings are available locally through eternas serial api, in addition to being available via the network manager. the performance characteristics of the temperature sensor can be found in the temperature sensor characteristics section.radio inhibit the radio_inhibit input enables an external controller to temporarily disable the radio software drivers ( for example, to take a sensor reading that is susceptible to radio interference). when radio_inhibit is asserted the software radio drivers will disallow radio operations including clear channel assessment, packet transmits, or packet receipts. if the radio is active in the current timeslot when radio_inhibit is asserted the radio will be diabled after the present operation completes. for details on the timing associated with radio_inhibit, see the radio_inhibit ac characteristics section. software installation devices are supplied with the flash erased, requiring pro - gramming as part of the oems manufacturing procedure . the us department of commerce places restrictions on export of systems and software supporting encryption . all of linear/dust product software produced to date contains encryption and is subject to export regulations and may be provided only via mylinear , https://www. linear.com/mylinear . customers purchasing smartmesh products will receive a certificate containing a registration key and registration instructions with their order. after registering with the key, customers will be able to download smartmesh software images from mylinear . once registered, customers will receive automated e-mail notifications as software updates are made available. linear technology offers the dc9010 , in circuit program - mer for the eterna based products. while the dc9010 , is provided as a finished product, the design documents are provided as a reference for customers. downloaded from: http:/// ltp 5901- ipm / ltp 5902- ipm 28 59012ipmfa for more information www.linear.com/ltp5901-ipm or www.linear.com/ltp5902-ipm operation once software has been loaded, devices can be configured via either the cli or api ports. configuration commands and settings are defined in smartmesh ip mote api guide and smartmesh ip mote cli guide . flash d ata retention eterna contains internal flash ( nonvolatile memory) to store calibration results, unique id, configuration settings and software images. flash retention over the operating temperature range. see electrical characteristics and absolute maximum ratings sections. non destructive storage above the operating temperature range of C40 c to 85 c is possible; although, this may result in a degradation of retention characteristics. the degradation in flash retention for temperatures >85 c can be approximated by calculating the dimensionless acceleration factor using the following equation. af = e ea k ?? ? ?? ? ? 1 t use + 273 ? 1 t stress + 273 ? ? ? ? ? ? ? ? ?? ? ? ?? where: af = acceleration factor ea = activation energy = 0.6ev k = 8.625 ? 10 C5 ev/k t use = is the specified temperature retention in c t stress = actual storage temperature in c example: calculate the effect on retention when storing at a temperature of 105c. t stress = 105c t use = 85c af = 2.8 so the overall retention of the flash would be degraded by a factor of 2.8, reducing data retention from 20 years at 85c to 7.1 years at 105c. state diagram in order to provide capabilities and flexibility in addition to ultralow power, eterna operates in various states, as shown in figure 11. eterna state diagram and described in this section. state transitions shown in red are not recommended.start-up start-up occurs as a result of either crossing the power-on reset threshold or asserting resetn. after the completion of power-on reset or the falling edge of an internally synchronized resetn, eterna loads its fuse table which, as described in the previous section, includes setting i/o direction. in this state, eterna checks the state of the flash_p_enn and resetn and enters the serial flash emulation mode if both signals are asserted. if the flash_p_enn pin is not asserted but resetn is asserted, eterna automatically reduces its energy consumption to a minimum until resetn is released. once resetn is de-asserted, eterna goes through a boot sequence, and then enters the active state.serial flash emulation when both resetn and flash_p_enn are asserted, eterna disables normal operation and enters a mode to emulate the operation of a serial flash. in this mode, its flash can be programmed.operation once eterna has completed start-up, eterna transitions to the operational group of states ( active/cpu active, active/ cpu inactive, and doze). there, eterna cycles between the various states, automatically selecting the lowest pos - sible power state while fulfilling the demands of network operation. active state in the active state, eternas relaxation oscillator is running and peripherals are enabled as needed. the arm cortex -m3 downloaded from: http:/// ltp 5901- ipm / ltp 5902- ipm 29 59012ipmfa for more information www.linear.com/ltp5901-ipm or www.linear.com/ltp5902-ipm figure 15. eterna state diagram load fuse settings resetn low and flash_p_enn high resetn high and flash_p_enn high reset deassert resetn cpu and peripherals inactive hw or pmu event boot start-up operation inactive doze deep sleep low power sleep command 59012ipm f15 assert resetn assert resetn assert resetn cpu active cpu inactive power-on reset resetn low and flash_p_enn low set resetn high and flash_p_enn high for 125s, then set resetn low vsupply > por active serial flash emulation operation cycles between cpu-active and cpu-inactive ( referred to in the arm cortex-m3 literature as sleep now mode). eternas extensive use of dma and intelligent peripherals that independently move eterna between active state and doze state minimizes the time the cpu is active, signifi - cantly reducing eternas energy consumption. doze state the doze state consumes orders of magnitude less cur - rent than the active state and is entered when all of the peripherals and the cpu are inactive. in the doze state eternas full state is retained, timing is maintained, and eterna is configured to detect, wake, and rapidly respond to activity on i/os ( such as uart signals and the timen pin). in the doze state the 32.768 khz oscillator and as - sociated timers are active. downloaded from: http:/// ltp 5901- ipm / ltp 5902- ipm 30 59012ipmfa for more information www.linear.com/ltp5901-ipm or www.linear.com/ltp5902-ipm operation i 2 c master the i 2 c master enables control of i 2 c slave devices, including support for clock stretching slaves. i 2 c multi- master and bus arbitration protocols are not supported. for implementation details refer to the on-chip software development kit (on-chip sdk) . spi masterthe eterna spi master controller supports all configurations of clock polarity and phase, supporting shift clock frequen - cies of 460.8 khz , 921.6 khz , 1.8432 mhz, or 3.6864 mhz . in addition the spi master controller can be configured to repetitively issue commands and capture the correspond - ing output, enabling repetitive sampling of signals from a spi adc or spi sensor based upon a clock reference of better than 50 ppm. for implementation details refer to the on-chip software development kit (on-chip sdk) . 1-wire master the eterna 1- wire master controller supports the reset, presence detect, read and write 1- wire protocol operations , incorporating an active pull - up . the active pull - up becomes active when the passive pull-up raises the voltage on the 1_wire pin nominally above 1.4 v, driving the 1_ wire signal as specified in digital i/o characteristics . for implementation details refer to the on-chip software development kit (on-chip sdk) . downloaded from: http:/// ltp 5901- ipm / ltp 5902- ipm 31 59012ipmfa for more information www.linear.com/ltp5901-ipm or www.linear.com/ltp5902-ipm applications information modes of operation the smartmesh ip mote software can be operated in three distinct modes, namely, namely slave, master, and on- chip sdk. mode selection should be considered during the architecture / design phase of the development process . slave mode in slave mode, the eterna is connected to an external microprocessor through the api uart and is solely used as a networking device. none of the built in i/os are ac - cessible in this mode. refer to the smartmesh ip user's guide for more detailed information. master mode in master mode, no external processor is required and a limited set of functionality is made available with no pro - gramming required on the device. the following features are available n on-chip temperature sensor n 4 analog inputs n 4 digital inputs n 3 digital outputs refer to the smartmesh ip user's guide for more detailed information.on-chip sdk (ocsdk) the smartmesh ip on - chip software development kit ( on - chip sdk ) enables development of c- code applications for execution on the ltc5800 - ipm, running micrium s cos - ii real-time operating system. with the on-chip sdk, users may quickly and easily develop application code without the need for an external microprocessor. applications written within the on-chip sdk may send and receive wireless messages through the mesh network ; process data, such as statistical analysis; execute local decision-making and control; and manage the following peripherals: n general purpose input-output (gpio) pins n analog-to-digital converter (adc) n universal asynchronous receiver / transmitter (uart) n serial peripheral interface (spi) master n inter-integrated circuit (i 2 c) master n 1- wire master network connectivity and quality of service is handled by the smartmesh ip protocol stack. the smartmesh ip stack comes as a pre-compiled library and delivers >99.999% data reliability while providing ultra low power operation. regulatory and standards compliance radio certification the lt p 5901 and lt p 5902 have been certified under a single modular certification, with the module name of eterna2. following the regulatory requirements pro - vided in the eterna2 users guide enables customers to ship products in the supported geographies, by simply completing an unintentional radiator scan of the finished product(s). the eterna2 users guide also provides the technical information needed to enable customers to further certify either the modules or products based upon the modules in geographies that have not or do not support modular certification.compliance to restriction of hazardous substances (rohs)restriction of hazardous substances 2 ( rohs 2) is a directive that places maximum concentration limits on the use of certain hazardous substances in electrical and electronic equipment. linear technology is committed to meeting the requirements of the european community directive 2011/65/eu. downloaded from: http:/// ltp 5901- ipm / ltp 5902- ipm 32 59012ipmfa for more information www.linear.com/ltp5901-ipm or www.linear.com/ltp5902-ipm applications information related documentation title location description smartmesh ip users guide http://www.linear.com/docs/41880 theory of operation for smartmesh ip networks and motes smartmesh ip mote api guide http://www.linear.com/docs/41886 definitions of the applications interface commands available over the api uart smartmesh ip mote cli guide http://www.linear.com/docs/41885 definitions of the command line interface commands available over the cli uart lt p 5901 and lt p 5902 hardware integration guide http://www.linear.com/docs/41877 recommended practices for designing with the lt p 5901 and lt p 5902 eterna2 users guide http://www.linear.com/docs/42916 the eterna2 module users guide includes certification requirements applicable to certified geographies and support documentation enabling customer certification in additional geographies for the lt p 5901 and lt p 5902 smartmesh ip tools guide http://www.linear.com/docs/42453 the users guide for all ip related tools, and specifically the definition for the on-chip application protocol (oap) this product has been specifically designed to utilize rohs-compliant materials and to eliminate or reduce the use of restricted materials to comply with 2011/65/eu.the rohs-compliant design features include: n rohs-compliant solder for solder joints n rohs-compliant base metal alloys n rohs-compliant precious metal plating n rohs-compliant cable assemblies and connector choices n rohs-compliant and 245c reflow compatible note: customers may elect to use certain types of lead- free solder alloys in accordance with the european com- munity directive 2011/65/ eu. depending on the type of solder paste chosen, a corresponding process change to optimize reflow temperatures may be required. soldering information the lt p 5901 and lt p 5902 are suitable for both eutectic pbsn and rohs-6 reflow. the maximum reflow solder - ing temperature is 260 c. a more detailed description of layout recommendations, assembly procedures and design considerations is included in the lt p 5901 and lt p 5902 hardware integration guide . downloaded from: http:/// ltp 5901- ipm / ltp 5902- ipm 33 59012ipmfa for more information www.linear.com/ltp5901-ipm or www.linear.com/ltp5902-ipm package description please refer to http:// www .linear.com/product/ lt p 5901#packaging for the most recent package drawings. pc package 66-lead pcb (24mm 42mm) (reference ltc dwg # 05-08-10002 rev a) r.010 0.25 typ .0391.00 typ .039 1.00 4x .035 0.90 .039 1.00 0 0.00 .08 2.00 .1574.00 .1975.00 .2366.00 .3448.74 .444 11.28 .551 14.00 .591 15.00 .630 16.00 .87 22.00 .728 18.50 .394 10.00 0 0.00 .08 2.00 .0391.00 .0391.00 .0792.00 1.10228.00 1.06327.00 1.03126.20 1.12228.50 1.21330.80 1.57 40.00 .0391.00 1.65442.00 .1002.54 .0391.00 .945 24.00 a 1 2 3 b appd: appd: prod rel date: proj mgr: chk: drn by: 4 5 6 do not scale dwg of 7 8 scale title dimensions are in inches engrg mgr: finish: d size material: tolerances 2 plc angles 3 plc approvals date: unless otherwise specified projection dwg no. rev. sheet a c d 1 2 3 c 4 5 6 description rev zone d approved date 7 revisions 8 rwb 1/27/13 061-0167 a 1/1 1 1 .01 .005 030' checker appd. approved program mgr: a release per eco 001203 1/29/13 rwb pca outline drawing, ltp 5901 30695 huntwood ave, hayward, ca 94544 the information contained in this drawing is the sole property of linear incorporated. any reproduction in part or as a whole without the written permission of linear incorporated is prohibited. proprietary and confidential lt p 5901 mechanical drawing downloaded from: http:/// ltp 5901- ipm / ltp 5902- ipm 34 59012ipmfa for more information www.linear.com/ltp5901-ipm or www.linear.com/ltp5902-ipm package description please refer to http:// www .linear.com/product/ lt p 5902#packaging for the most recent package drawings. pc package 66-lead pcb (24mm 37.5mm) (reference ltc dwg # 05-08-10003 rev a) .0391.00 typ r.010 0.25 typ .039 1.00 .039 1.00 4x .035 0.90 0 0.00 .078 2.0 .1574.00 .1975.00 .2366.00 .3448.73 .444 11.28 .866 22.00 .394 10.00 0 0.00 .0792.01 .0391.00 .0391.00 .0792.00 1.03126.20 1.21330.80 1.40 35.50 1.12228.50 1.10228.00 1.27232.30 1.06327.00 .0711.80 .728 18.50 .551 14.00 .591 15.00 .630 16.00 1.47637.50 .0391.00 .0290.73 .1002.54 .0391.00 .1774.50 .945 24.00 a 1 2 3 b appd: appd: prod rel date: proj mgr: chk: drn by: 4 5 6 do not scale dwg of 7 8 scale title dimensions are in inches engrg mgr: finish: d size material: tolerances 2 plc angles 3 plc approvals date: unless otherwise specified projection dwg no. rev. sheet a c d 1 2 3 c 4 5 6 description rev zone d approved date 7 revisions 8 rwb 1/27/13 061-0176 1 1/1 1 1 .01 .005 030' checker appd. approved program mgr: 1 release per eco 001203 1/29/13 rwb pca outline drawing, ltp 5902 30695 huntwood ave, hayward, ca 94544 proprietary and confidential the information contained in this drawing is the sole property of linear technology corporation. any reproduction in part or as a whole without the written permission of linear technology corporation is prohibited. lt p 5902 mechanical drawing downloaded from: http:/// ltp 5901- ipm / ltp 5902- ipm 35 59012ipmfa for more information www.linear.com/ltp5901-ipm or www.linear.com/ltp5902-ipm information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. revision history rev date description page number a 11/15 updated ordering part number added on-chip sdk sectionadded software installation section 5 23, 30, 31 27 downloaded from: http:/// ltp 5901- ipm / ltp 5902- ipm 36 59012ipmfa for more information www.linear.com/ltp5901-ipm or www.linear.com/ltp5902-ipm ? linear technology corporation 2014 lt 1115 rev a ? printed in usa linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax : (408) 434-0507 www.linear.com/ltp5901-ipm or www.linear.com/ltp5902-ipm related parts typical application part number description comments ltc5800-ipm ip wireless mote ultralow power mote, 72-lead 10mm 10mm qfn lt p 5901-ipr ip wireless mesh manager pcb module with chip antenna includes modular radio certification in the united states, canada, europe, japan, south korea, taiwan, india, australia and new zealand lt p 5902-ipr ip wireless mesh manager pcb module with mmcx antenna connector includes modular radio certification in the united states, canada, europe, japan, south korea, taiwan, india, australia and new zealand lt6654 precision high output drive low noise reference 1.6ppm peak-to-peak noise (0.1hz to 10hz, sink/source 10ma, 5ppm/c max drift ltc2379-18 18-bit,1.6msps/1msps/500ksps/250ksps serial, low power adc 2.5v supply, differential input, 101.2db snr, 5v input range, dgc ltc3388-1/ltc3388-3 20v high efficiency nanopower step-down regulator 860na i q in sleep, 2.7v to 20v input, v out = 1.2v to 5v, enable and standby pins ltc3588-1 piezoelectric energy generator with integrated high efficiency buck converter v in = 2.7v to 20v, v out(min) = fixed to 1.8v/2.5v/3.3v/3.6v, i q = 0.95a, 3mm 3mm dfn-10 and msop-10e packages ltc3108-1 ultralow v oltage step-up converter and power manager v in = 0.02v to 1v, v out = 2.5v/3v/3.7v/4.5v fixed, i q = 6a, 3mm 4mm dfn-12 and ssop-16 packages ltc3459 micropower synchronous boost converter v in = 1.5v to 5.5v, v out(max ) = 10v, i q = 10a, 2mm 2mm dfn, 2mm 3mm dfn or sot-23 package mesh network thermistor 59012ipm ta02 tadiran tl-5903 li-soci 2 ltp5902-ipm antenna vsupply ipcs_miso ai_0ai_1 0.1f gnd lt6654 5k 0.1% 10k, 0.2comega 4406 v in v out gnd2 gnd1 0.1f 1000pf 5k 0.1% 5k0.1% 1000pf rt = 5k ? ai_0 / (2 ? ai_1 C ai_0) t(c) = 1 / {a + b [ln(rt)] + c[ln(rt)] 3 } C 273.15 a = 1.032 ? 10 C3 b = 2.387 ? 10 C4 c = 1.580 ? 10 C7 downloaded from: http:/// |
Price & Availability of LTP5901IPC-IPMA1D0PBF
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |